In magnetoresistive RAM (MRAM) data is stored as magnetic polarization in elements called magnetic tunnel junctions (MTJs). The resistance depends on the relative polarization of two layers in the MTJ. One layer is permanent (“fixed”) while the other (“free”) layer will change to match that of a sufficiently strong external field. By measuring the resistance, the free layer polarization can be determined. A memory device may be built from a grid of such “cells” incorporating MTJs.
Alternatively, spin-transfer-torque (STT) MRAM uses spin-aligned (“polarized”) electrons of sufficient critical current density to directly torque and “write” the polarization to the free layer, where the polarization direction and junction resistance depend on the direction of electron flow. A sub-critical current density can be used to measure the resistance. This write current further decreases as the memory cell size scales down, which is a critical benefit as the Si technology continues to scale to higher device pitch density.
A memory state is determined by whether the free and fixed layer polarizations are parallel or anti-parallel. In the parallel state (“0-State”), the tunneling resistance across the thin insulating layer is relatively “low.” In the anti-parallel state, the tunneling resistance across the thin insulating layer is relatively “high.” Measuring this magnetoresistance determines the memory state stored in the MTJ cell.
A metric for characterizing the two resistance values is called the magnetization ratio (MR), defined as the difference between the MTJ anti-parallel resistance (Rap) and the MTJ parallel resistance (Rp), divided by the MTJ parallel resistance (Rp), i.e., (Rap−Rp)/Rp. It is preferable that the MR be as large as possible, i.e., that the resistance values of the two states be as far apart as possible, to ensure the reliability of correctly reading the memory state of an MTJ cell.
Measuring the memory state may be accomplished, for example, as follows: An MRAM cell may conventionally include an MTJ and a transistor in series between a bit line and a source line. The bit line and source line are set at a potential difference. When the transistor gate is set on (e.g., “high”), current can flow through the MTJ. The current is defined by the net potential difference and the series sum of bit line resistance, MTJ resistance, transistor on state resistance and source line resistance. The MTJ resistance can have one of two values: “low” for the parallel 0-State, or “high” for the anti-parallel 1-State. By measuring the voltage drop across the MTJ and the current passing through the MTJ cell, the resistance may be computed. A reference voltage, e.g., between the MTJ-transistor junction and the source line, may be compared to the voltage measured with the MTJ in either of two states. Setting the reference voltage to a value intermediate between the two measured voltages may be used in a comparator logic gate to distinguish the two states.
Due to variations in processing conditions that may normally occur in the course of device fabrication, and even variations across the extent of a single chip containing many such MTJ cells in a memory array (due, for example, to lithography uniformity), variations in the value of the magnetoresistance may result. This becomes increasingly important when device structures scale to dimensions on the order of tens of nanometers or less, and the process variations are on the order of nanometers. That is, when the fractional change in device dimensions become significant relative to the device size, the possibility exists that process variations may result in the magnetoresistance of some MTJ cells in the low 0-State becoming close to or overlapping with the magnetoresistance of some MTJ cells in the high 1-State. Since the resistance value is conventionally determined by measuring a voltage drop across the MTJ cell and comparing it to the reference voltage, errors in reading the memory state of the MTJ cell may occur.
In a large memory array of MTJ cells, the number of memory read errors may become significant due to process variation and temperature (PVT). In conjunction with automated test equipment (ATE), 100% testing of all memory elements is possible.
Because the total of all resistances occurring from all sources apart from the MTJ, i.e., “parasitic” resistance, may be comparable to the MTJ resistance, the total measurable difference in resistance between the two MTJ states may be a significant fraction (e.g., 25%-75%) of the total resistance. A larger parasitic resistance dilutes the change in voltage measured between the two resistance states of the MTJ, as described above, which may limit the margins for setting a resistance reference level for distinguishing which state the MTJ is in, i.e., whether the resistance is lower than the reference (an average of Rp and Rap), or higher than the reference.
Moreover, ATE, cables to interface the ATE and the memory chip, and on-chip interconnects may introduce additional parasitic resistances and reactive impedances. Such parasitics may be significant compared to the impedance of a nanoscale MTJ MRAM device and this may limit the accuracy and speed of testing.
There is a need, therefore, to be able to characterize the statistical variation of magnetoresistance in both states of MTJ cells in a memory array, both as a means of characterizing process stability, and in determining parallel resistance and anti-parallel resistance reference levels for reading memory states, that can cancel out or compensate for parasitic effects.